Approximate bit-loading for data transmission over frequency-selective channels

ABSTRACT

A high-speed communications system utilizes approximate bit-loading during data transmission in a channel. In one embodiment, a plurality of parallel data preparation circuits in a data transmission circuit receive respective subsets of a data stream, each of the respective subsets of the data stream having a data rate that is less than a data rate of the data stream. Converters in the data preparation circuits convert the respective subsets of the data stream into respective analog signals. Multipliers in the data preparation circuits multiply the respective analog signals by respective vectors to produce respective sub-channel signals. At least a frequency band in the spectrum corresponding to one of the respective sub-channel signals partially overlaps at least a frequency band for at least one other of the respective sub-channel signals. The respective sub-channel signals are combined prior to transmission.

BRIEF DESCRIPTION OF THE INVENTION

The present invention relates generally to the communication of data. More specifically, the present invention relates to the communication of data over frequency-selective channels.

BACKGROUND OF THE INVENTION

Low bit-error-rate communication of data over a communications channel is an important requirement in communications systems. Fulfilling this requirement is increasingly difficult in high-speed communications systems with data rates exceeding multiple Gbits/s. In the case of an interface between semiconductor chips or dies, there is the additional problem associated with the highly frequency-selective transfer function of the communications channel. For lower speed communications systems, such as digital subscriber line (xDSL) and wireless local area network (WLAN) technologies, solutions for this problem include bit-loading and multiple-carrier communications techniques. These approaches achieve higher data rates over a communications channel with a frequency-selective transfer function through an improved utilization of the available bandwidth. In particular, the available bandwidth is divided into multiple frequency sub-bands (the multiple-carrier principle) and more information is transmitted in those sub-bands that suffer less attenuation and less information is transmitted in those sub-bands that suffer more attenuation (the bit-loading principle). There are several existing implementations of bit-loading and multiple-carrier communications techniques.

FIG. 1 illustrates one implementation of these techniques, an analog multi-tone system 100. During data transmission, respective subsets 110 a-110 m (collectively 110), of a data stream are converted to analog signals in digital-to-analog (D/A) converters 120 a-120 m (collectively 120). The analog signals are multiplied in multipliers 126 a-126 m (collectively 126) by sinusoids having different frequencies and phases provided by sinusoid generators 130 a-130 m (collectively 130) to produce respective sub-channel signals. In the frequency domain, the spectrum corresponding to the analog signals is therefore shifted to frequency sub-bands centered on the different carrier frequencies. The respective sub-channel signals are then filtered using steep band-pass filters 140 a-140 m (collectively 140) to ensure precise bit-loading. The respective sub-channel signals are then combined by a summing or other combining circuit 150 and transmitted through a channel 152.

FIG. 4 a illustrates the magnitude 510 as a function of frequency 520 of the spectrum 500 corresponding to the respective sub-channel signals in precise bit-loading. The overlap of a first frequency band 530 and a second frequency band 540 is such that any signal loss due to the overlap is substantially less than the noise floor. For example, the amount of power in the first frequency band 530 that overlaps the second frequency band 540 may be less than 1 percent, and in many implementations is less than 0.1 percent. The amount of overlap, if any, depends on the implementation, the frequency selectivity of the channel 152 and a target data rate. In this document, frequency bands with power overlaps of less than 1 percent are considered to not overlap. In this illustration, there is a gap 550 between the first frequency band 530 and the second frequency band 540.

Referring back to FIG. 1, during data receiving, signals transmitted through the channel 152 are filtered by steep bandpass filters 154 a-154 m (collectively 154 ). The resulting respective sub-channel signals are multiplied in multipliers 160 a-160 m (collectively 160) by sinusoids having different frequencies and phases provided by sinusoid generators 170 a-170 m (collectively 170) to produce respective analog signals. The respective analog signals are integrated in integrators 174 a-174 m (collectively 174) to produce respective integrated analog signals. Conversion of the respective integrated analog signals by analog-to-digital (A/D) converters 180 a-180 m (collectively 180) produces respective subsets 190 a-190 m (collectively 190) of the data stream. When the system 100 is operating properly, subsets 190 a-190 m are substantially the same, and preferably substantially identical, to subsets 110 a-110 m.

The analog multi-tone system 100, however, is difficult and expensive to implement in high-speed communications systems including those with data rates exceeding multiple Gbits/s. The steep bandpass filters 140 and 154 are the primary obstacles in realizing this technique at high data rates. There is a need, therefore, for an improved bit-loading technique for data transmission in high-speed communications systems.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating an existing analog multi-tone system.

FIG. 2 is a block diagram illustrating an embodiment of the approximate bit-loading technique.

FIG. 3 is a block diagram illustrating another embodiment of the approximate bit-loading technique.

FIG. 4 a is a schematic illustrating the spectrum in existing precise bit-loading techniques.

FIG. 4 b is a schematic illustrating the spectrum in an embodiment of the approximate bit-loading technique.

FIG. 5 is a flow diagram illustrating an embodiment of the transmission of data in the approximate bit-loading technique.

FIG. 6 is a flow diagram illustrating an embodiment of the receiving of data in the approximate bit-loading technique.

FIG. 7 is a block diagram illustrating an embodiment of the approximate bit-loading technique.

FIG. 8 is a block diagram illustrating an embodiment of the approximate bit-loading technique.

FIG. 9 is a block diagram illustrating an embodiment of the approximate bit-loading technique.

Like reference numerals refer to corresponding parts throughout the drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In one embodiment of the present invention, a plurality of parallel data preparation circuits in a data transmission subsystem receive respective subsets of a data stream, the respective subsets of the data stream each having a data rate that is substantially less than a data rate of the data stream. Converters in the data preparation circuits convert the respective subsets of the data stream into respective analog signals. Multipliers in the data preparation circuits multiply the respective analog signals by respective vectors to produce respective sub-channel signals. The respective vectors correspond to sequences of N elements. Each of the respective vectors is orthogonal to the respective vectors used by the multipliers in each of the other data preparation circuits during a finite time interval corresponding to each of the sequences of N elements. The respective sub-channel signals are combined prior to transmission.

In an additional embodiment, a plurality of parallel data receiving circuits in a data receiving subsystem receive a common input signal. Multipliers in the data receiving circuits multiply the common input signal by respective vectors to produce respective sub-channel signals. The respective vectors correspond to sequences of N elements. Each of the respective vectors is orthogonal to the respective vectors used by the multipliers in each of the other data preparation circuits during a finite time interval corresponding to each of the sequences of N elements. Integrators in each of the data receiving circuits integrate the respective sub-channel signals to produce respective integrated sub-channel signals, the respective integrated sub-channel signals each having a data rate that is substantially less than a data rate of the common input signal. Converters in the data receiving circuits convert the respective integrated sub-channel signals into digital signals.

Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

FIG. 2 illustrates a system 300 for an embodiment of the approximate bit-loading technique. During data transmission, respective subsets 310 a-310 n (collectively 310) of a data stream are coupled to a plurality of parallel data preparation circuits 304 a-304 n (collectively 304) in a data transmission subsystem 302 (also herein called the data transmission circuit). Each of the respective subsets 310 of the data stream has a data rate that is substantially less, e.g., 10 percent to 95 percent less, than a data rate of the data stream. The data rates of the respective subsets 310 will depend on the number of subsets and how the bits of the data stream are distributed over the subsets 310. In some embodiments, each of the subsets 310 has a data rate that is at least 50 percent less than the data rate of the data stream.

Digital-to-analog (D/A) converters 320 a-320 n (collectively 320) convert the respective subsets 310 of the data stream into respective analog signals. The respective analog signals are multiplied in multipliers 330 a-330 n (collectively 330) by respective vectors 340 a-340 n (collectively 340) to produce respective sub-channel signals. The number (n) of vectors 340 and data preparation circuits 304 may vary from one implementation to another. In some embodiments, the number is at least two and less than or equal to thirty-two.

The respective vectors 340 correspond to sequences of N elements. Each of the respective vectors 340 is orthogonal to the respective vectors 340 used by the multipliers 330 in each of the other data preparation circuits during a finite time interval corresponding to each of the sequences of N elements. The respective sub-channel signals are combined in a combiner 350, e.g., an analog summing circuit, prior to transmission through a channel 352.

As in the analog multi-tone system 100 shown in FIG. 1, multiplying the respective analog signals by the respective vectors 340 in the system 300 shifts the spectrum corresponding to the analog signals. In contrast with previous approaches, however, the elimination of bandpass filters and the characteristics of the respective vectors 340 in the system 300 results in substantial overlap of the frequency bands in the spectrum. This is illustrated in FIG. 4 b, which shows the magnitude 510 as a function of frequency 520 of a spectrum 560 corresponding to the respective sub-channel signals. There is an overlap 590 of a first frequency band 570 and a second frequency band 580. The orthogonality of the respective vectors 340, however, ensures that respective sub-channel signals can be extracted from the combined signals received by data receiving subsystems 303 (FIG. 2).

In general, the spectrum 560 corresponding to one of the respective sub-channel signals may contain a group of frequency bands. In the context of the approximate bit-loading embodiments described here, a substantial overlap 590 exists for at least one of those frequency bands and at least one frequency band corresponding to another of the respective sub-channel signals. In this context, a substantial overlap is defined to mean that the amount of power in the first frequency band 570 that overlaps the second frequency band 580 is greater than 5 percent, and in many implementations is greater than or equal to 10 percent. The amount of overlap 590, if any, depends on the implementation, the frequency selectivity of the channel 352 (FIG. 2) and the target data rate.

In the system 300 (FIG. 2), the spectrum 560 corresponding to the respective sub-channel signals may be adjusted by using bit-to-symbol coding, where one or more bits are mapped together to a multi-level symbol in the respective subsets 310 of the data stream (FIG. 2) such that some of the respective subsets 310 (FIG. 2) convey more information per unit time than others. For example, a group of two bits can be mapped to one of four different amplitudes of a voltage pulse signal, one of four different phases of a sinusoid or a combination of one of two different amplitudes of a sinusoid and one of two different phases of the same sinusoid. For example if the initial data stream has ten bits per time unit (e.g., nanosecond), and those ten bits are allocated to eight data preparation circuits 304, with six of the circuits 304 each receiving a single bit per time unit and two of the circuits 304 each receive two bits per time unit, the latter two data preparation circuits 304 will each perform a two-bit to symbol coding. Furthermore, the D/A conversion rate for all eight of the data preparation circuits 304 will be one tenth of the aggregate data rate.

Each of the respective subsets 310 (FIG. 2) of the data stream has a data rate that is less than the data rate of the data stream. In this way, the spectrum 560 corresponding to the respective sub-channel signals and thus the signals transmitted may be adjusted to appropriately match the transmission characteristics of the channel 352 (FIG. 2), including one with a highly frequency-selective transfer function. In an alternate embodiment, the spectrum 560 may be adjusted by allocating or demultiplexing bits at different data rates for at least one of the respective subsets 310 of the data stream (FIG. 2).

The transfer function of the channel 352 (FIG. 2) may be characterized initially, e.g., determined during by a calibration process, and the spectrum 560 may be set to a desired form and subsequently fixed. Alternatively, a training sequence may be transmitted by the data transmission circuit to determine the transfer function of the channel 352 (FIG. 2) and the spectrum 560 may be adjusted to the desired form using a feedback mechanism, for example, by adjusting the bit-to-symbol coding in the respective subsets 310 of the data stream (FIG. 2).

FIG. 5 is a flow chart 600 of the data transmission process used in some embodiments. Subsets of the data stream are received 610. These are converted 620 to analog signals. The analog signals are multiplied 640 by respective vectors 630 to produce respective sub-channel signals. The respective sub-channel signals are combined 650 and transmitted 660. It may be noted that performing the digital to analog conversion 620 prior to multiplying 640 the subset signals by the respective vectors results in a lower D/A conversion rate than if these operations were performed in the opposite order. Because very high rate D/A converters are more expensive than lower rate D/A converters, this methodology reduces the cost of the circuitry required to implement this data transmission methodology. Note that this methodology results in a D/A conversion rate which is at least n times lower than the aggregate data rate of system 300 (FIG. 2), where n is the number of subsets 310 of the data stream (FIG. 2).

Referring back to FIG. 2, during data receiving a common input signal is coupled to a plurality of data receiving circuits 362 a-362 n (collectively 362) in the data receiving subsystem 303. The common input signal is multiplied using multipliers 360 a-360 n (collectively 360) in the data receiving circuits 362 by respective vectors 370 a-370 n (collectively 370) to produce respective sub-channel signals. Once again, the respective vectors 370 correspond to the sequences of N elements. In some embodiments, each of the respective vectors 370 is the same as a corresponding vector 340 in the data transmission subsystem 302. Each of the respective vectors 370 is orthogonal to the respective vectors 370 used by the multipliers 360 in each of the other data receiving circuits 362 during the finite time interval corresponding to each of the sequences of N elements. Integrators 380 a-380 n (collectively 380) in each of the data receiving circuits 362 integrate the respective sub-channel signals for a length of time (also known as an integration period) corresponding to the finite time interval to produce respective integrated sub-channel signals, each of the respective integrated sub-channel signals having a data rate that is less than a data rate of the common input signal. In some embodiments, the integrators 380 are implemented using so-called integrate and dump circuits. In some embodiments, the integrators 380 are reset after each integration period. The integrators 380 transfer the respective integrated sub-channel signals to analog-to-digital (A/D) converters 390 a-390 n (collectively 390), which convert the respective integrated sub-channel signals into respective subsets 400 a-400 n (collectively 400) of the data stream. When the data transmission subsystem 302 and the data receiving subsystem 303 are operating properly, the recovered subsets 400 are substantially the same as the corresponding data sets 310.

FIG. 6 is a flow chart 700 of the data receiving process used in some embodiments. A common input signal is received 710. The common input signal is multiplied 720 by respective vectors 730 to produce respective sub-channel signals. The respective sub-channel signals are integrated 740 to produce respective integrated sub-channel signals. In some embodiments, the integration is reset or dumped after each integration period. The respective integrated sub-channel signals are converted 750 into digital signals. Noted that performing the A/D conversion 750 after multiplying 720 the common input signal by the respective vectors and integrating 740 the respective sub-channel signals results in a A/D conversion rate which is at least n times lower than the aggregate data rate of the system 300 (FIG. 2).

Referring back to FIG. 2, the characteristics of the respective vectors 340 and 370 used by the data transmission subsystem 302 and the data receiving subsystem 303 are the same and described below. Mathematically, each of the respective subsets 310 and 400 of the data stream may be represented by a train of pulses ${{d_{i}(t)} = {\sum\limits_{n = {- \infty}}^{\infty}\quad{{{d_{i}\lbrack n\rbrack} \cdot g}\quad\left( {t - {nTsym}} \right)}}},$ where d_(i)[n] are the samples of one of the respective subsets 310 and 400 of the data stream arriving once every Tsym seconds and g(t) is a function having any suitable shape, for example, a rectangular pulse of duration Tsym. Each of the respective vectors 340 and 370 may be represented by ${{c_{i}(t)} = {\sum\limits_{n = {- \infty}}^{\infty}\quad{\sum\limits_{m = 0}^{N - 1}\quad{{{H_{i}\lbrack m\rbrack} \cdot p}\quad\left( {t - {nTsym} - {mTchip}} \right)}}}},$ where H_(i)[m] is an element in one of the sequences with a number of elements N and p(t) is a rectangular pulse of unity height and duration Tchip. Note that each of the respective vectors 340 and 370 cyclically repeats with a period Tsym. Also note that Tsym may be an integer multiple of Tchip. In an exemplary embodiment, Tsym equals N times Tchip.

From this description, in one embodiment the respective vectors 340 and 370 may be analog signals based on the sequences. In an alternative embodiment, the multiplication in the data transmission and data receiving circuits may use a digital representation of the respective vectors 340 and 370.

In another embodiment, an inverse of the data rate of the data stream may be an integer multiple of a bit time, i.e., Tsym, for each of the respective subsets 310 and 400 of the data stream. The integer multiple may be an even integer. In an exemplary embodiment, the integer multiple is N.

In yet another embodiment, the finite time over which the respective vectors 340 and 370 in FIG. 2 are orthogonal to other respective vectors 340 and 370, and the finite time that the integrators 380 integrate the respective sub-channel signals may correspond to, or be substantially equal to N times a bit time, i.e., Tchip, for the respective vectors 340 and 370. In addition, the inverse of the data rate of the common input signal may be an integer multiple of a bit time of the respective vectors 340 and 370. The integer multiple may be an even integer. In an exemplary embodiment, the integer multiple is N.

Each element of the sequences of N elements may be binary numbers and each element of the respective vectors 340 and 370 may correspond to one of two voltage levels. In an exemplary embodiment, each of the sequences corresponds to a row of a Hadamard matrix of order N, where the number of elements N in a row is an even integer. The N value chosen is limited by the overall latency and circuit complexity, i.e., the number of parallel data preparation 304 and data receiving 306 circuits. A binary Hadamard matrix of order 8 (i.e., N equal to 8) represents a reasonable tradeoff between latency, circuit complexity, the overlap 590 (FIG. 4) of the frequency bands in the spectrum 560 (FIG. 4) and the data rate of the respective subsets 310 and 400 of the data stream (and, thus, the speed of D/A converters 320 and A/D converters 390). In this exemplary embodiment, the integrators 380 may integrate the respective sub-channel signals for the finite time, corresponding to 8 times Tchip, before transferring the respective integrated sub-channel signals to a next circuit.

Some embodiments may use sequences with non-binary elements and respective vectors 340 and 370 with elements having more than two voltage levels. This will, however, make the multiplication of the respective analog signals and the respective vectors 340 and the common input signal and the respective vectors 370 more complex. As an example, each element of the sequences may be ternary numbers and each element of the respective vectors 340 and 370 may correspond to one of three voltage levels. Other suitable sequences include binary pseudorandom sequences such as maximal length sequences (m-sequences), Gold codes and Kasami sequences.

Several alternative embodiments are shown in the system 401 in FIG. 3. Pre-emphasis filters 426 a-426 n (collectively 426) may be included in each of the data preparation circuits 404 of the data transmission subsystem 402. At the data receiving subsystem 403, the common input signal may be equalized with an equalizer 454. In addition, equalizers 482 a-482 n (collectively 482) may be placed in each of the data receiving circuits 462 a-462 n (collectively 462). The equalizers 454 and 482 may be implemented as feed-forward filters, as decision feedback equalization circuits, or as a combination of both.

In an alternative embodiment, the pre-emphasis filters 426 may be combined into a single pre-emphasis block 326, with one or more of the outputs from the D/A converters 320 as inputs to the pre-emphasis block 326, as shown in FIG. 7. Referring back to FIG. 3, in an alternative embodiment pre-emphasis may be applied to the data stream prior to the D/A conversion of the respective subsets 310 of the data stream. In an additional embodiment, the pre-emphasis filters 426 may be combined with the D/A converters 320.

In an additional embodiment, equalization in the data receiving subsystem 403 may be implemented using the equalizers 482 in the data receiving circuits 462, but without using equalizer 454. Alternatively, equalization may be implemented using only equalizer 454, without using equalizers 482. In an additional embodiment, equalization may be implemented using equalizers 482 with both the respective sub-channel signals and the digital outputs 400 as inputs, using optional feedback 392, as shown in FIG. 3. Referring to FIG. 7, in an additional embodiment equalization may be implemented using a single equalizer 394 with one or more of the respective sub-channel signals and, optionally, one or more of the digital outputs 400 as inputs.

Referring to FIG. 8, in some embodiments a timing recovery mechanism 396 in data receiving subsystem 803 may determine synchronization information from the common input signal and couple the synchronization information to at least one of the integrators 380 and at least one of the A/D converters 390. Typically, the synchronization information would be used to control each of the integrators 380 and each the A/D converters 390. The synchronization information from the timing recovery mechanism 396 may also adjust a phase of at least one of the signal generators 910 that generates the respective vectors corresponding to sequences of N elements (thereby allowing the phase of one or more of the respective vectors to be adjusted). In some embodiments, the signal generators 910 may be implemented as a single signal generator. In yet another embodiment, the data receiving circuits 362 (FIG. 2) and 462 (FIG. 3) may receive synchronization information from the timing recovery mechanism 396 based on an optional clock input signal 912 from an external source and the common input signal.

FIG. 9 illustrates a plurality of timing recovery mechanisms 398 that may be included in the data receiving circuits 914 and may determine synchronization information from the respective sub-channel signals and couple the synchronization information to the respective integrators 380, A/D converters 390 and/or signal generators 910. Coupling the synchronization information to the signal generators 910 allows the phase of the respective vectors to be adjusted. In some embodiments, the plurality of timing recovery mechanisms 398 may determine synchronization information from the respective integrated sub-channel signals.

Phase differences between at least two of the sub-channel signals may develop due to dispersion in the channel 352. These phase differences may be mitigated by adjusting the synchronization information. Specifically, phase differences between at least two of the respective sub-channel signals may be mitigated by varying the phase of at least one of the respective vectors multiplying the common input signal by modifying the synchronization information to one of the signal generators 910.

By allowing substantial overlap 590 (FIG. 4 b) of the frequency bands in the spectrum 560 (FIG. 4 b) of the respective sub-channel signals, the approximate bit-loading technique described herein eliminates the steep bandpass filters 140 and 154 (FIG. 1). This approximate bit-loading technique allows the advantages of bit-loading, such as roughly matching the spectrum 560 (FIG. 4 b) of the respective sub-channels to the highly frequency-selective transfer functions of a communications channel 352 (FIG. 2), to be employed in high-speed communications systems.

The approximate bit-loading apparatus and method are well-suited for use in the interface between semiconductor chips or dies, such as electronic interconnects. In particular, the approximate bit-loading apparatus and method are well-suited for use in improving communication between semiconductor chips on the same printed circuit board (PCB) or between semiconductor chips on different printed circuit boards that are connected through a backplane or a coaxial cable at data rates exceeding multiple Gbit/s. The approximate bit-loading apparatus and method are also well-suited for use in improving communication between a memory controller chip and a dynamic random access memory (DRAM) chip. The DRAM chip may be either on the same printed circuit board as the controller or embedded in a memory module. In addition, the approximate bit-loading apparatus and method are also well-suited for use in improving communication at data rates exceeding multiple Gbit/s between a buffer chip and a DRAM chip, both of which are on the same memory module. The apparatus and methods described herein may also be applied to other memory technologies, such as static random access memory (SRAM) and electrically erasable programmable read-only memory (EEPROM).

The foregoing descriptions of specific embodiments of the present invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Rather, it should be appreciated that many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. 

1. A data transmission circuit, comprising: a plurality of parallel data preparation circuits, each data preparation circuit including: a converter configured to receive a respective subset of a data stream and to convert the respective subset of the data stream into a respective analog signal, wherein the respective subset of the data stream has a respective data rate substantially less than a data rate of the data stream; and a multiplier for multiplying the respective analog signal by a respective vector to produce a respective sub-channel signal, wherein the respective vector corresponds to a sequence of N elements and the respective vector used by the multiplier in each of the plurality of data preparation circuits is substantially orthogonal to respective vectors used by multipliers in each of the other data preparation circuits, and wherein the respective vectors are substantially orthogonal during a finite time interval corresponding to each sequence of N elements; and a combiner for combining respective sub-channel signals prior to transmission.
 2. The data transmission circuit of claim 1, wherein the finite time interval is substantially equal to N times a bit time for the respective vector.
 3. The data transmission circuit of claim 1, wherein an inverse of the data rate of the data stream is an integer multiple of a bit time of the respective subset of the data stream.
 4. The data transmission circuit of claim 1, wherein N is an even integer.
 5. The data transmission circuit of claim 1, wherein each element of each sequence is a binary number and each element of the respective vectors corresponds to one of two voltage levels.
 6. The data transmission circuit of claim 1, wherein each respective sub-channel signal corresponds to at least one frequency band that at least partially overlaps a frequency band for at least one other respective sub-channel signal.
 7. The data transmission circuit of claim 1, wherein each respective sub-channel signal corresponds to a group of frequency bands at least one of which substantially overlaps a frequency band for at least one other respective sub-channel signal.
 8. The data transmission circuit of claim 1, wherein the sequence corresponds to a row of a Hadamard matrix of order N.
 9. The data transmission circuit of claim 1, further comprising one or more pre-emphasis filters in the data transmission circuit.
 10. The data transmission circuit of claim 1, further comprising a multiple-input, multiple-output pre-emphasis filter in the data transmission circuit.
 11. A data receiving subsystem, comprising: a plurality of parallel data receiving circuits, each having an input coupled to a input node for receiving a common input signal, each data receiving circuit including: a multiplier for multiplying the common input signal by a respective vector to produce a respective sub-channel signal, wherein the respective vector corresponds to a sequence having N elements and the respective vector used by the multiplier in each of the plurality of data receiving circuits is substantially orthogonal to respective vectors used by the multipliers in each of the other data receiving circuits, and wherein the respective vectors are substantially orthogonal during a finite time interval corresponding to each sequence of N elements; an integrator for integrating the respective sub-channel signal to produce a respective integrated sub-channel signal, wherein the respective integrated sub-channel signal has a data rate substantially less than a data rate of the common input signal; and a converter configured to convert the respective integrated sub-channel signal into a digital signal.
 12. The data receiving subsystem of claim 11, wherein the integrator integrates the respective sub-channel signal for substantially the finite time interval.
 13. The data receiving subsystem of claim 11, wherein an inverse of the data rate of the common input signal is an integer multiple of a bit time of the respective vector.
 14. The data receiving subsystem of claim 11, wherein the finite time interval is substantially equal to N times a bit time for the respective vector.
 15. The data receiving subsystem of claim 11, wherein N is an even integer.
 16. The data receiving subsystem of claim 11, wherein each element of each sequence is a binary number and each element of the respective vectors corresponds to one of two voltage levels.
 17. The data receiving subsystem of claim 11, wherein the respective sub-channel signal corresponds to at least one frequency band that at least partially overlaps a frequency band for at least one other respective sub-channel signal.
 18. The data receiving subsystem of claim 11, wherein the respective sub-channel signal corresponds to a group of frequency bands at least one of which substantially overlaps a frequency band for at least one other respective sub-channel signal.
 19. The data receiving subsystem of claim 11, wherein the sequence corresponds to a row of a Hadamard matrix of order N.
 20. The data receiving subsystem of claim 11, further comprising a receiver equalization filter after the input node and before the input of each of the data receiving circuits.
 21. The data receiving subsystem of claim 11, further comprising a plurality of receiver equalization filters, including a respective receive equalization filter in each of the data receiving circuits.
 22. The data receiving subsystem of claim 11, further comprising a single multiple-input, multiple-output equalization filter coupled to the converter of at least two of the parallel data receiving circuits.
 23. The data receiving subsystem of claim 11, further comprising a timing recovery mechanism coupled to the input node and to at least one converter and one integrator in one of the data receiving circuits, whereby the timing recovery mechanism determines synchronization information from the common input signal.
 24. The data receiving subsystem of claim 11, further comprising a plurality of timing recovery mechanisms, including a respective timing recovery mechanism coupled to each of the data receiving circuits and to the converter and the integrator in the data receiving circuit.
 25. The data receiving subsystem of claim 24, wherein the respective timing recovery mechanism for a particular data receiving circuit determines synchronization information from the corresponding respective integrated sub-channel signal.
 26. The data receiving subsystem of claim 11, further comprising a clock circuit configured to receive a clock input signal from an external source that also generates the common input signal using the clock input signal.
 27. A method of transmitting data, comprising: receiving a plurality of subsets of a data stream, wherein each of the respective subsets of the data stream has a respective data rate substantially less than a data rate of the data stream; converting each of the respective subsets of the data stream into respective analog signals; multiplying each of the respective analog signals by a respective vector to produce a respective sub-channel signal, wherein the respective vector corresponds to a sequence having N elements and the respective vector is substantially orthogonal to respective vectors used for multiplying each of the other respective analog signals, and wherein the respective vectors are substantially orthogonal during a finite time interval corresponding to each sequence of the N elements; and combining the respective sub-channel signals prior to transmission.
 28. The method of transmitting data in claim 27, wherein the finite time interval is substantially equal to N times a bit time for the respective vector.
 29. The method of transmitting data in claim 27,wherein an inverse of the data rate of the data stream is an integer multiple of a bit time of each of the respective subsets of the data stream.
 30. The method of transmitting data in claim 27, wherein N is an even integer.
 31. The method of transmitting data in claim 27, wherein each element of each sequence is a binary number and each element of the respective vectors corresponds to one of two voltage levels.
 32. The method of transmitting data in claim 27, wherein each respective sub-channel signal corresponds to at least one frequency band that at least partially overlaps a frequency band for at least one other respective sub-channel signal.
 33. The method of transmitting data in claim 27, wherein each respective sub-channel signal corresponds to a group of frequency bands at least one of which substantially overlaps a frequency band for at least one other respective sub-channel signal.
 34. The method of transmitting data in claim 27, wherein the sequence corresponds to a row of a Hadamard matrix of order N.
 35. The method of transmitting data in claim 27, further comprising pre-emphasizing each of the respective subsets of the data stream prior to converting each of the respective subsets of the data stream into the respective analog signals.
 36. The method of transmitting data in claim 27, further comprising coding respective subsets of the data stream using a bit-to-symbol code such that respective subsets of the data stream convey different amounts of information per unit time than other respective subsets of the data stream, thereby producing a spectrum corresponding to the resulting respective sub-channel signals that substantially corresponds to a transfer function of a communications channel.
 37. The method of transmitting data in claim 27, further comprising allocating portions of the data stream to form the respective subsets of the data stream such that spectral content of resulting respective sub-channel signals substantially corresponds to a transfer function of a transmission channel.
 38. The method of transmitting data in claim 27, further comprising demultiplexing the data stream to form the respective subsets of the data stream such that spectral content of resulting respective sub-channel signals substantially corresponds to a transfer function of a transmission channel.
 39. A method of receiving data, comprising: receiving a common input signal; multiplying the common input signal by a plurality of respective vectors to produce a plurality of respective sub-channel signals, wherein each of the respective vectors corresponds to a sequence having N elements and each of the respective vectors is substantially orthogonal to the other respective vectors, and wherein the respective vectors are substantially orthogonal during a finite time interval corresponding to each sequence of N elements; integrating each of the respective sub-channel signals to produce respective integrated sub-channel signals, wherein each of the respective integrated sub-channel signals has a data rate substantially less than a data rate of the common input signal; and converting each of the respective integrated sub-channel signals into a digital signal.
 40. The method of receiving data of claim 39, wherein integrating each of the respective sub-channel signals occurs for substantially the finite time interval.
 41. The method of receiving data of claim 39, wherein an inverse of the data rate of the common input signal is an integer multiple of a bit time for each of the respective vectors.
 42. The method of receiving data of claim 39, wherein the finite time interval is substantially equal to N times a bit time for each of the respective vectors.
 43. The method of receiving data of claim 39, wherein N is an even integer.
 44. The method of receiving data of claim 39, wherein each element of each sequence is a binary number and each element of the respective vectors corresponds to one of two voltage levels.
 45. The method of receiving data of claim 39, wherein at least one of the respective sub-channel signals corresponds to at least one frequency band that at least partially overlaps a frequency band for at least one other of the respective sub-channel signals.
 46. The method of transmitting data in claim 39, wherein at least one of the respective sub-channel signals corresponds to a group of frequency bands at least one of which substantially overlaps a frequency band for at least one other of the respective sub-channel signals.
 47. The method of receiving data of claim 39, wherein the sequence corresponds to a row of a Hadamard matrix of order N.
 48. The method of receiving data of claim 39, further comprising equalizing the common input signal prior to multiplying the common input signal by the plurality of respective vectors.
 49. The method of receiving data of claim 39, further comprising equalizing each of the respective integrated sub-channel signals.
 50. The method of receiving data of claim 39, further comprising recovering synchronization information from the common input signal.
 51. The method of receiving data of claim 39, further comprising recovering synchronization information from each of the respective integrated sub-channel signals.
 52. The method of receiving data of claim 51, further comprising correcting for phase differences between at least two of the respective integrated sub-channel signals by adjusting the synchronization information determined from at least one of the corresponding respective integrated sub-channel signals.
 53. The method of receiving data of claim 39, further comprising correcting for phase differences between at least two of the respective sub-channel signals by varying the phase of at least one of the respective vectors multiplying the common input signal.
 54. The method of receiving data of claim 39, further comprising receiving a clock input signal from an external source that also generates the common input signal using the clock input signal.
 55. A data transmission subsystem, comprising: a mechanism configured to receive a plurality of respective subsets of a data stream, to convert each of the respective subsets of the data stream into respective analog signals, to multiply each of the respective analog signals by one of a plurality of respective vectors to produce respective sub-channel signals and to combine the respective sub-channel signals prior to transmission; wherein each of the respective subsets of the data stream has a respective data rate substantially less than a data rate of the data stream, an inverse of the data rate of the data stream is an integer multiple of a bit time of each of the respective subsets of the data stream, each of the respective vectors corresponds to one of a plurality of sequences of binary numbers with a number of elements N that is an even integer, each element of the respective vectors corresponds to one of two voltage levels, each of the respective vectors is substantially orthogonal to other respective vectors during a finite time interval of N times a bit time for each of the respective vectors, and each of the respective sub-channel signals corresponds to at least one frequency band that at least partially overlaps a frequency band for at least one other of the respective sub-channel signals.
 56. The data transmission subsystem of claim 55, wherein the sequence corresponds to a row of a Hadamard matrix of order N.
 57. A data receiving subsystem, comprising: a mechanism configured to receive a common input signal, to multiply the common input signal by a plurality of respective vectors to produce a plurality of respective sub-channel signals, to integrate the respective sub-channel signals to produce respective integrated sub-channel signals and to convert the respective integrated sub-channel signals into digital signals, wherein an inverse of the data rate of the common input signal is an integer multiple of a bit time of each of the respective vectors, each of the respective vectors corresponds to one of a plurality of sequences of binary numbers with a number of elements N that is an even integer, each element of the respective vectors corresponds to one of two voltage levels, each of the respective vectors is substantially orthogonal to other respective vectors during a finite time interval of N times a bit time for each of the respective vectors, each of the respective sub-channel signals is integrated for substantially the finite time interval, each of the respective sub-channel signals corresponds to at least one frequency band that at least partially overlaps a frequency band for at least one other of the respective sub-channel signals and each of the respective integrated sub-channel signals has a data rate substantially less than a data rate of the common input signal.
 58. The data receiving subsystem of claim 57, wherein the sequence corresponds to a row of a Hadamard matrix of order N. 